The present invention relates to an input signal level detecting circuit made up of CMOS-FET's (complementary metal oxide semiconductor field effect transistors), and more particularly to an input signal level detecting circuit well adapted for an arrangement of a Schmitt trigger circuit.
Since the input signal level detecting circuit according to the present invention is suitable for the Schmitt trigger circuit, the present invention will be described with relation to the Schmitt trigger circuit. A typical example of prior Schmitt trigger circuits is disclosed in Japanese patent publication No. 25755/53 (1978). The Schmitt trigger circuit disclosed will briefly be described with reference to FIG. 1. In FIG. 1, an input signal is supplied to an inverter circuit 2 made up of CMOS transistors, through an input terminal 1. The Schmitt trigger circuit further contains a set-reset flip-flop circuit (RS F/F) 5 in which two-input NAND gate circuits 3 and 4 comprised of CMOS transistors are arranged as shown. A set terminal S is connected to an output terminal of the inverter circuit 2, while a reset terminal R is connected to the input terminal 1. A set output Q is derived from a terminal 6, while a reset output Q is derived from a terminal 7. In the circuit, the single inverter circuit 2 is provided between the input terminal 1 and the set terminal S of the RS F/F so that the threshold voltage of the inverter circuit 2 during the rise time of the input signal is higher than that of the inverter circuit 2 during the fall time of the input signal. With this arrangement, the output voltage of the inverter circuit 2 has a hysteresis characteristic. Those threshold voltages in the rise and fall times of the input signal changes depend on a manufacturing condition of the CMOS's, so that the threshold voltages frequently have great deviations from their set values. This results in a change of the hysteresis voltage width in the output of the inverter 2. As shown, the inverter circuit 2 is inserted only between the input signal terminal 1 and the set input terminal 8 of the RS F/F. Therefore, it is difficult to freely set the threshold voltages of the inverter 2 for the rise and fall times of the input signal. Therefore, the Schmitt trigger circuit as shown in FIG. 1 is not suitable if a large hysteresis voltage width is required.